This invention relates generally to signal packet communication networks and more especially to multi-user communication systems, e.g. TDMA/FDMA satellite communication systems, where each user is assigned a time slot and a frequency slot at which he is allowed to transmit.
In a multi-user TDMA/FDMA satellite communication system, for instance, where several users access the satellite channel and send through signal packets according to some slotted access scheme, a hub ground station at the receiving end receives the stream of signal packets from many users and it recovers the original user information messages by demodulating and detecting the packets. In order to perform demodulation and detection, the hub station needs to estimate the signal timing and the frequency offset for each received signal packet.
The conventional techniques for timing and frequency estimation are based on tracking loops performing a closed-loop estimation. However, when the number of users is larger than the number of frequency slots and when the traffic is bursty, i.e. when the time between two consecutive packets from the same user is long with respect to the duration of a packet, it is difficult, if not impossible, for the hub station to track the timing and frequency offsets for each user, from packet to packet. Then, the hub station must be able to estimate the timing and frequency offsets independently for each received packet by some open-loop processing. In order to accomplish this task, the hub station receiver must be equipped with a synchronization sub-system which implements a fast, real-time and reliable open-loop timing and frequency estimation process.
A first approach consists in performing the timing and frequency estimations separately for each signal packet. First, the signal is oversampled (the number of symbols Ns is greater than the number M of samples per symbol) over a window of L symbols. Thereafter, the whole packet is decimated by a factor M/Ns and the frequency offset is estimated on the resulting decimated signal.
This method has the following drawbacks:
(a) in order to achieve a timing estimation error variance sufficiently small, the oversampling factor Ns/M must be at least 4, PA1 (b) the computational load for the timing estimation is of the order of N.sup.2.sub.s log Ns, PA1 (c) the processing can be applied with a reasonable complexity only for binary or quaternary FSK modulation (M.ltoreq.4), PA1 (d) the frequency estimation process has a threshold value of signal-to-noise ratio for which the estimation error variance approaches its ideal value, at roughly 10 dB of Eb/No in the absence of timing errors.
The invention aims at overcoming the drawbacks mentioned above.